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Features
* Six High-side and Six Low-side Drivers * Outputs Freely Configurable as Switch, Half Bridge or H-bridge * Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors * * * * * * * * * * * *
and Inductors 0.6 A Continuous Current per Switch Low-side: RDSon < 1.5 W versus Total Temperature Range High-side: RDSon < 2.0 W versus Total Temperature Range Very Low Quiescent Current Is < 20 A in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40 V Daisy Chaining Possible SO28 Power Package
40-V Dual Hex Output Driver with Serial Input Control T6816
Description
The T6816 is a fully protected driver interface designed in 0.8 m BCDMOS technology. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build Hbridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Overvoltage protection is matched to the requirements of the 24-V industrial voltage and the 24-V automotive supply. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications.
Rev. 4595B-BCD-05/03
1
Figure 1. Block Diagram
HS1
15
HS2
15
13
HS3
13
12
HS4
12
HS5 3
3
HS6 22
28
28
Fault Detect
Fault Detect
Fault Detect
Fault Detect
Fault Detect
Fault Detect
5
VS VS
10
DI
26 6
GND
Osc
CLK
25 S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 7
GND
VS
CS
24
Input Register Output Register
P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P
Control logic
8
UV protection Thermal protection Power-on reset
GND
9
GND
INH
17
20
GND
18
DO
21
GND
Vcc
Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect
22
GND
23
GND
Vcc
19
Vcc
16
14
11
4
1
27
LS1
LS2
LS3
LS4
LS5
LS6
2
T6816
4595B-BCD-05/03
T6816
Pin Configuration
Figure 2. Pinning SO28
HS6 28
LS6 27
DI 26
CLK 25
CS 24
GND GND GND GND VCC DO 23 22 21 20 19 18
INH 17
LS1 HS1 16 15
T6816
Lead frame 1 LS5 2 HS5 3 HS4 4 LS4 5 VS 6 7 8 9 10 VS 11 LS3 12 HS3 13 HS2 14 LS2
GND GND GND GND
Pin Description
Pin
1 2 3 4 5 6, 7, 8, 9 10 11 12 13 14 15 16 17
Symbol
LS5 HS5 HS4 LS4 VS GND VS LS3 HS3 HS2 LS2 HS1 LS1 INH
Function
Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 4; see Pin 2 Low-side driver output 4; see Pin 1 Power supply output stages HS4, HS5, HS6, internal supply; external connection to Pin 10 necessary Ground; reference potential; internal connection to Pin 20 - 23; cooling tab Power supply output stages HS1, HS2 and HS3 Low-side driver output 3; see Pin 1 High-side driver output 3; see Pin 2 High-side driver output 2; see Pin 2 Low-side driver output 2; see Pin 1 High-side driver output 1; see Pin 2 Low-side driver output 1; see Pin 1 Inhibit input; 5 V logic input with internal pull down; low = standby, high = normal operating Serial data output; 5 V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the C (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Logic supply voltage (5 V) Ground; see Pin 6 - 9 Chip select input; 5 V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial clock input; 5 V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Serial data input; 5 V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Low-side driver output 6; see Pin 1 High-side driver output 6; see Pin 2
18 19 20, 21, 22, 23 24 25
DO VCC GND CS CLK
26 27 28
DI LS6 HS6
3
4595B-BCD-05/03
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3. Data Transfer Input Data Protocol
CS
DI
SRR 0 1
LS1
HS1 2 3
LS2
HS2 4 5
LS3
HS3 6 7
LS4
HS4 8 9
LS5
HS5 10
LS6 11
HS6 12
OLD 13
SCT 14
SI 15
CLK
DO
TP
SLS1
SHS1
SLS2
SHS2
SLS3
SHS3
SLS4
SHS4
SLS5
SHS5
SLS6
SHS6
SCD
INH
PSF
Table 1. Input Data Protocol
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12
Input Register
SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1
4
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4595B-BCD-05/03
T6816
Table 1. Input Data Protocol (Continued)
Bit
13 14
Input Register
OLD SCT
Function
Open load detection (low = on) Programmable time delay for short circuit (shutdown delay high/ low = 12 ms/1.5 ms Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered)
15
SI
Table 2. Output Data Protocol
Bit
0
Output (Status) Register
TP
Function
Temperature prewarning: high = warning (overtemperature shutdown see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17). High = standby, low = normal operation
1
Status LS1
2
Status HS1
3 4 5 6 7 8 9 10 11 12 13
Status LS2 Status HS2 Status LS3 Status HS3 Status LS4 Status HS4 Status LS5 Status HS5 Status LS6 Status HS6 SCD
14 15 Note:
INH
PSF Power supply fail: undervoltage at Pin VS detected Bit 0 to 15 = high: overtemperature shutdown
Table 3. Status of the Input Register after Power on Reset
Bit 15 (SI) Bit 14 (SCT) Bit 13 (OLD) Bit 12 (HS6) Bit 11 (LS6) Bit 10 (HS5) Bit 9 (LS5) Bit 8 (HS4) Bit 7 (LS4) Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR)
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
5
4595B-BCD-05/03
Power Supply Fail
In case of undervoltage at Pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS-VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the openload function for this output. If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, T j switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
Open-load Detection
Overtemperature Protection
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-6 , ILS1-6 ) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. There are two ways to inhibit the T6816: 1. Set bit SI in the input register to zero 2. Switch Pin 17 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by Pin 17 (INH) switched back to 5 V.
Inhibit
6
T6816
4595B-BCD-05/03
T6816
Absolute Maximum Ratings
All values refer to GND pins
Parameter
Supply voltage Pins 5, 10 Supply voltage tt0.5 s; ISu-2 A Pins 5, 10 Supply voltage difference |VS_Pin5 - VS_Pin10| Supply current Pins 5, 10 Supply current t < 200 ms Pins 5, 10 Logic supply voltage Pin 19 Input voltage Pin 17 Logic input voltage Pins 24 to 26 Logic output voltage Pin 18 Input current Pins 17, 24 to 26 Output current Pin 18 Output current Pins 1 to 4, 11 to 16, Pins 27 and 28 Reverse conducting current Pins 2, 3, 12, 13, 15, (tPulse = 150 ms) 28 towards Pins 5, 10 Junction temperature range Storage temperature range
Symbol
VVS VVS DVVS IVS IVS VVCC VINH VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO ILS1 to ILS6 IHS1 to IHS6 IHS1 to IHS6 Tj TSTG
Value
-0.3 to +40 -1 150 1.4 2.6 -0.3 to +7 -0.3 to +17 -0.3 to VVCC +0.3 -0.3 to VVCC +0.3 -10 to +10 -10 to +10 Internal limited, see output specification 17 -40 to +150 -55 to +150
Unit
V V mV A A V V V V mA mA
A C C
Thermal Resistance
All values refer to GND pins
Parameter
Junction - pin Junction ambient
Test Conditions
Measured to GND Pins 6 to 9 and 20 to 23
Symbol
RthJP RthJA
Min.
Typ.
Max.
25 65
Unit
K/W K/W
Operating Range
All values refer to GND pins
Parameter
Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Note: 1. Threshold for undervoltage detection.
Test Conditions
Pins 5, 10 Pin 19 Pin 17, 24 to 26 Pin 25
Symbol
VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj
Min.
VUV (1) 4.5 -0.3
Typ.
5
Max.
40 5.5 VVCC 2
Unit
V V V MHz C
-40
150
7
4595B-BCD-05/03
Noise and Surge Immunity
Parameter
Conducted interferences Interference Suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5: VSmax = 40 V
Test Conditions
ISO 7637-1 VDE 0879 Part 2 MIL-STD-883D Method 3015.7 EOS/ESD - S 5.2
Value
Level 4 (1) Level 5 2 kV 150 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No. 1
1.1 1.2 1.3 Supply current (VS) 1.4 Supply current (VS) 1.5
Parameters Current Consumption
Quiescent current (VS) Quiescent current (VCC)
Test Conditions
VVS < 28 V, INH or bit SI = lo 4.5 V < VVCC < 5.5 V, INH or bit SI = low VVS < 28 V normal operating, all output stages off, VVS < 28 V normal operating, all output stages on, no load 4.5 V < VVCC < 5.5 V, normal operating Pin
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5, 10 19
IVS IVCC IVS 0.8
40 20
A A
A A
5, 10
1.2
mA
A
5, 10
IVS IVCC
10
mA
A
Supply current (VCC)
19
150
A
A
2
2.1
Internal Oscillator Frequency
Frequency (timebase for delay timers) fOSC 19 45 kHz A
3
3.1 3.2 3.3 3.4 3.5
Undervoltage Detection, Power-on Reset
Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay After switching on VVCC 19 19 5, 10 5, 10 5, 10 VVCC tdPor VUV DVUV tdUV 7 3.4 30 5.5 0.4 21 3.9 95 4.4 160 7.0 V s V V ms A A A A A
4
4.1 4.2
Thermal Prewarning and Shutdown
Thermal prewarning Thermal prewarning 17 17 TjPWset TjPWreset 125 105 145 125 165 145 C C A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
8
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4595B-BCD-05/03
T6816
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No.
4.3 4.4 4.5 4.6 4.7
Parameters
Thermal prewarning hysteresis Thermal shutdown Thermal shutdown Thermal shutdown hysteresis Ratio thermal shutdown/thermal prewarning Ratio thermal shutdown/thermal prewarning
Test Conditions
Pin
Symbol
DTjPW
Min.
Typ.
20
Max.
Unit
K
Type*
A A A A
17 17
Tj switch off Tj switch on DTj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset
150 130
170 150 20
190 170
C C K
1.05
1.17
A
4.8
1.05
1.2
A
5
5.1
Output Specification (LS1 - LS6, HS1 - HS6) 7.5 V < VVS < 40 V
On resistance IOut = 600 mA 1, 4, 11, 14, 16, 27 2, 3, 12, 13, 15, 28 1, 4, 11, 14, 16, 27 1, 4, 11, 14, 16, 27 2, 3, 12, 13, 15, 28 1-4, 11-16 27, 28 1-4, 11-16 27, 28 1, 4, 11,14 16, 27 A RDS OnL 1.5 W
5.2 On resistance IOut = -600 mA
A RDS OnH 2.0 W
5.3 Output clamping voltage 5.4 Output leakage current 5.5 Output leakage current 5.7 VHS1-6 = 0 V all output stages off VLS1-6 = 40 V all output stages off ILS1-6 = 50 mA
VLS1-6
40
60
V
A
A ILS1-6 10 A
A IHS1-6 -10 A
Inductive shutdown energy Output voltage edge steepness Overcurrent limitation and shutdown threshold
Woutx
15
mJ
D
5.8
dVLS1-6/dt dVHS1-6/dt ILS1-6
50
200
400
mV/s
A
5.9
650
950
1250
mA
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
9
4595B-BCD-05/03
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No.
5.10
Parameters
Overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Open load detection current Open load detection current Open load detection current ratio Open load detection threshold Open load detection threshold Output switch on delay 1) Output switch off delay 1)
Test Conditions
Pin
2, 3, 12,13 15, 28
Symbol
IHS1-6
Min.
-1250
Typ.
-950
Max.
-650
Unit
mA
Type*
A
5.11 5.12
Input register bit 14 (SCT) = low Input register bit 13 (OLD) =low, output off Input register bit 13 (OLD) =low, output off 1, 4, 11,14 16, 27 2, 3, 12, 13 15, 28
tdSd ILS1-6
1.0
1.5
2.0
ms
A
60
200
A
A
5.13
IHS1-6 ILS1-6/IHS1-
6
-150
-30
A
A
5.14 5.15
1.2
A
Input register bit 13 (OLD) =low, output off Input register bit 13 (OLD) =low, output off RLoad = 1 kW RLoad = 1 kW
1, 4, 11,14 16, 27 2, 3, 12, 13 15, 28
VLS1-6 VVS- VHS1-6 tdon tdoff
0.6
4
V
A
5.16
0.6
4
V
A
5.17 5.18
0.5 1
ms ms
A A
6
6.1 6.2 6.3 6.4
Inhibit Input
Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current Input voltage lowlevel threshold Input voltage highlevel threshold Hysteresis of input voltage Pull-down current Pin DI, CLK Pull-up current Pin CS VDI, VCLK = VVCC VCS= 0 V VINH = VVCC 17 17 17 17 VIL VIH DVI IPD 100 10 0.3VVCC 0.7VVCC 50 2 -50 500 50 -2 0.3VVCC 0.7VVCC 700 80 V V mV A A A A A
7
7.1 7.2 7.3 7.4 7.5
Serial Interface - Logic Inputs DI, CLK, CS
24-26 24-26 24-26 25, 26 24 VIL VIH DVI IPDSI IPUSI V V mV A A A A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
10
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4595B-BCD-05/03
T6816
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No. 8
8.1 8.2 8.3
Parameters
Output voltage low level Output voltage high level Leakage current (tri-state)
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Serial Interface - Logic Output DO
IOL = 3 mA IOL = -2 mA VCS = VVCC, 0 V < VDO < VVCC 18 18 18 VDOL VDOH IDO VVCC0.7 V -10 10 0.5 V V A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
Serial Interface -- Timing
Parameters
DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Input register Bit 14 (SCT) = high Input register Bit 14 (SCT) = low
Test Conditions
CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF
Timing Chart No.
1 2 - - 10 4 8 9 9 5 6 - 7 3 11 12
Symbol
tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold
Min.
Typ.
Max.
200 200 100 100 200
Unit
ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns
225 225 16 2 225 225 500 225 225 40 40
11
4595B-BCD-05/03
Figure 4. Serial Interface Timing with Chart Numbers
1 2
CS
DO
9
CS
4
7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12
T6816
4595B-BCD-05/03
T6816
Figure 5. Application Circuit
Vcc
U5021M WATCHDOG
Trigger Reset
Enable
HS1 15 HS2 13 HS3 12 HS4 HS5 HS6
3
2
28
Vs
BYT41
Fault Detect Fault Detect Fault Detect Fault Detect
Fault Detect
Fault Detect
5V S VS
GND
D
VBAT
24V
DI
26
6 Osc
S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R
CLK
25
S I
7
GND
mC
VS
Control logic
UV protection Thermal protection Power-on Reset
8 9
20 21 22 23
GND
CS
24
Input Register Output Register
P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P
GND
INH
17
GND
18
DO
GND
Vcc
Fault Detect Fault Detect Fault Detect Fault Detect
GND
Fault Detect
Fault Detect
GND
Vcc Vcc
16 LS1 14 LS2 11 LS3 LS4
19
Vcc 5V
4
LS5
1
27 LS6
Vs
Vs
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolut Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins.
4595B-BCD-05/03
+
Vcc Vcc
10
+ +
13
Ordering Information
Extended Type Number
T6816-TIQ
Package
SO28
Remarks
Power package, taped and reeled
Package Information
Package SO28
Dimensions in mm
18.05 17.80
9.15 8.65 7.5 7.3
2.35 0.4 1.27 28 16.51 15 0.25 0.10 0.25 10.50 10.20
technical drawings according to DIN specifications
1
14
14
T6816
4595B-BCD-05/03
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4595B-BCD-05/03 xM

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